Advanced Package Technology Principal Engineer

31 MSI

Not Interested
Bookmark
Report This Job

profile Job Location:

Austin, TX - USA

profile Monthly Salary: Not Disclosed
Posted on: 30+ days ago
Vacancies: 1 Vacancy

Job Summary

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

The Marvell Advanced Packaging R&D team is responsible for package design and
technology development to meet the electrical mechanical thermal and system
requirements for the next generation high performance computing (HPC) Artificial
Intelligence (AI) and networking solutions. The group focuses on signal integrity
power integrity thermal integrity mechanical integrity processability
manufacturability and reliability involving high speed signaling and complex power delivery networks (PDNs) requiring innovative and custom solutions to meet constantly evolving customer needs. Many of the new designs require multi-chip multiple component configurations involving but not limited to 2.5D and 3D packages Co-packaged copper or optics and advanced substrates. Marvell has partnered with the worlds leading manufacturers to solve our customers most challenging designs and integrations with industry-leading packaging technologies.

What You Can Expect

  • Own the packaging technology roadmap for AI XPU XPU-attach and Switch
  • Define system-level package architecture including chiplet topology interposer/substrate scaling power delivery network strategy and thermal design envelope.
  • Architect and evaluate packaging technology choices including silicon/glass interposers EMIB/bridge hybrid bonding fan-out and 3D stacking.
  • Lead co-design efforts across silicon design floorplanning PDN modeling and mechanical/thermal reliability.
  • Work with stakeholders to define and validate advanced design rule roadmap for interposer substrates and packages.
  • Work with vendors to define and validate equipment process and material
  • roadmap.
  • Explore technologies beyond what is currently available make recommendations and create and protect IP to maximize performance.
  • Explore technology feasibility and create proof-of-concept samples.
  • Collaborate with IP Si design package design production and test teams.
  • Lead package material selection substrate stack-up definition mechanical modeling and reliability analysis.
  • Partner with silicon design teams to co-optimize die floorplan bump map TSV and RDL requirements.
  • Support HBM integration strategy (HBM2E / HBM3 / HBM3E) with interposer or bridge-based designs.
  • Work with OSATs / Foundry partners to evaluate process capability manufacturability yield and cost.
  • Perform signal and power integrity trade-off analysis in partnership with SI/PI teams.
  • Drive package qualification and reliability validation to volume readiness

What Were Looking For

  • Experience in advanced package and substrate technologies with deep understanding of process and materials component and board level reliability warpage and thermal management.

  • Experience in managing substrate and assembly material vendors substrate manufacturers OSATs and foundries.

  • Bachelors degree in Mechanical Engineering Material Science Electrical Engineering or related fields and 10 years of related professional experience. OR Masters degree and/or PhD in Electrical Engineeringechanical Engineering Material Science or related fields with 5 years of experience.

Skills needed to be successful in this role:

  • Deep understanding of advanced 2.5D/3D package technology including (a) CoWoS-S/R/L (b) EMIB (c) CPO (d) CPC.

  • Strong understanding of chip-package interactions and failure mechanism at component and board level thermal and warpage management.

  • Ability to manage programs involving cross-functional teams. Strong interpersonal skills and willingness to learn new things are necessary along with the ability to work with stakeholders in multiple time zones across the globe.

  • Ability to influence suppliers to align their roadmap with company goals.

  • Strong communication presentation and documentation skills

The ideal candidate would have:

  • Experience setting roadmaps not just executing them.

  • Demonstrated leadership driving cross-company supplier programs.

  • Prior experience in data center AI accelerators networking silicon or custom HPC silicon.

  • Ability to influence senior stakeholders across architecture silicon design system platform engineering and supply chain

  • Understanding of component (substrate interposer etc.) and package designs.

  • Knowledge of signal integrity and power integrity.

  • Board and system level integration.

  • Experience with silicon disaggregation and reaggregation and memory integration.

Expected Base Pay Range (USD)

148500 - 219780 $ per annum

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell we offer a total compensation package with a base bonus and and financial wellbeing are part of the package. That means flexible time off 401k plus a year-end shutdown floating holidays paid time off to volunteer. Have a question about our benefits packages - health or financial Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.

#LI-MM1

Required Experience:

Staff IC

About Marvell Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.At Marvell you can affect the arc of individual lives ...
View more view more

Key Skills

  • Design
  • Academics
  • AutoCAD 3D
  • Cafe
  • Fabrication
  • Java

About Company

Designed for your current needs and future ambitions, Marvell delivers the data infrastructure technology transforming tomorrow’s enterprise, cloud, automotive, and carrier architectures for the better.

View Profile View Profile