Principal Physical Design Engineer

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

• Provide technical direction coaching and mentoring to employees on your team and others to achieve successful project outcomes

• Perform synthesis floor planning place and route timing analysis/closure and DRC/LVS cleanup on complex logic blocks

• Develop and implement timing closure and logical ECOs

• Write scripts in Perl Python and TCL to extract data and achieve productivity enhancements through automation

• Work with a variety of teams to pull in their required portion of the design such as DFT and clock distribution teams

• Leading a small group of engineers ensuring they are progressing meeting milestones on schedule and quality and providing on-time correct deliverables

• Work with the global timing team in debugging/resolving any block level timing issues seen at full chip

• Test and maintain chip end-to-end flows with specific focus on place and route integration and timing

• Interact with tool vendors to drive tool fixes and improvements in support of on-going and planned CAD activities

• Perform tool evaluations of new vendor tools and functions

What Were Looking For

• Bachelors degree in Computer Science Electrical Engineering or related fields and 5-10 years of related professional experience or Masters degree and/or PhD in Computer Science Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree

• 7 years of practical experience in physical design at all levels of hierarchy with multiple ASICs/SOCs

• Strong physical design knowledge and experience from RTL or netlist handoff to GDS tape-out

• Proficient in running chip/sub-system/partition level signoff including physical verification (DRC and LVS) along with power integrity (EMIR)

• Experienced in leading a team of block-level engineers coordinating at the sub-system/partition level

• Experience with partition/sub-section timing closure is a plus

• Track record of collaboration with RTL team

• Good knowledge of Verilog/VHDL is preferred

• Good understanding of digital logic and architecture

• Proficient in LINUX and shell-based scripting

• Solid knowledge and experience with TCL language

• Diligent detail-oriented and able to handle assignments with minimal supervision

• Must possess good communication skills be a self-driven individual and a good team player

• Open to candidates meeting requirements of Sr. Staff Engineer (T4)

• This role requires full-time on-site presence at our Westborough MA office five days a week. If you are not currently located in the area relocation will be necessary. Please note that remote or alternate work locations are not available for this position.

  Relocation assistance may be available for qualified candidates.

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.