Develop and maintain internal EDA tools and frameworks for RTL assembly and connectivity efficient algorithms for hierarchical RTL construction module binding and interface consistency across complex intelligent connectivity visualization and debug with front-end design DFT and integration teams to align methodologies and define tool automation and performance improvements including runtime optimization and scalability across large adoption documentation and user training for internal design teams.
- BSc/MSc in Electrical Engineering Computer Engineering or Computer Science
- 3 years of experience in FE design or integration
- Good programming skills in Python and C/C
- Solid understanding of RTL design (Verilog/SystemVerilog) and SoC integration concepts
Develop and maintain internal EDA tools and frameworks for RTL assembly and connectivity efficient algorithms for hierarchical RTL construction module binding and interface consistency across complex intelligent connectivity visualization and debug with front-end design DFT and integration teams ...
Develop and maintain internal EDA tools and frameworks for RTL assembly and connectivity efficient algorithms for hierarchical RTL construction module binding and interface consistency across complex intelligent connectivity visualization and debug with front-end design DFT and integration teams to align methodologies and define tool automation and performance improvements including runtime optimization and scalability across large adoption documentation and user training for internal design teams.
- BSc/MSc in Electrical Engineering Computer Engineering or Computer Science
- 3 years of experience in FE design or integration
- Good programming skills in Python and C/C
- Solid understanding of RTL design (Verilog/SystemVerilog) and SoC integration concepts
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