The ideal candidate should have a strong background in RTL and DV integration within SoC environments with hands-on experience in AMD design and verification flows particularly using DVLEC and Formality.
Should be proficient in System Verilog UVM C and C with a solid understanding of SoC architecture interconnects and subsystem integration.
Experience with
version control systems build flows and EDA tool chains is essential along with excellent
problem-solving debugging and communication skills.
The ideal candidate should have a strong background in RTL and DV integration within SoC environments with hands-on experience in AMD design and verification flows particularly using DVLEC and Formality. Should be proficient in System Verilog UVM C and C with a solid understanding of SoC architectu...
The ideal candidate should have a strong background in RTL and DV integration within SoC environments with hands-on experience in AMD design and verification flows particularly using DVLEC and Formality.
Should be proficient in System Verilog UVM C and C with a solid understanding of SoC architecture interconnects and subsystem integration.
Experience with
version control systems build flows and EDA tool chains is essential along with excellent
problem-solving debugging and communication skills.
View more
View less