DV Power Management
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Job Location:
Monthly Salary:
Posted on:
15 days ago
Vacancies:
1 Vacancy
Job Summary
8yrs
The role involves verification of power management features at the SoC level focusing on ensuring functional correctness and robustness of power gating (PG) and other low-power mechanisms.
The candidate will be responsible for power-aware verification using UPF (Unified Power Format) validating power domains isolation strategies retention and sequencing across the SoC.
Hands-on expertise in C C SystemVerilog (SV) and UVM is required to develop and enhance testbench components create power-aware test scenarios and debug complex SoC-level interactions.
The position demands a strong understanding of SoC power architecture low-power design concepts and verification methodologies to ensure comprehensive coverage and high-quality silicon results
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