8yrs
The role involves working across GDP (Graphics Data Path) and CDP (Core Data Path) subsystems with hands-on experience in USB4 (USB 4.0) LPDDR5 PCIe and Ethernet interfaces at the SoC level. The candidate should possess strong expertise in SystemVerilog (SV) UVM C and C with a solid understanding of SoC design integration and verification methodologies
8yrs The role involves working across GDP (Graphics Data Path) and CDP (Core Data Path) subsystems with hands-on experience in USB4 (USB 4.0) LPDDR5 PCIe and Ethernet interfaces at the SoC level. The candidate should possess strong expertise in SystemVerilog (SV) UVM C and C with a solid understand...
8yrs
The role involves working across GDP (Graphics Data Path) and CDP (Core Data Path) subsystems with hands-on experience in USB4 (USB 4.0) LPDDR5 PCIe and Ethernet interfaces at the SoC level. The candidate should possess strong expertise in SystemVerilog (SV) UVM C and C with a solid understanding of SoC design integration and verification methodologies
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