RTL Design Engineer
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Job Location:
San Francisco, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
18 days ago
Vacancies:
1 Vacancy
Job Summary
In this role you will work on a small team dedicated to IP architecture design and verification. As a member of the team you will be asked to architect and design new modules while working with multiple cross-functional teams including: Design Integration Platform Architecture Software Engineering DFT and Debug. You will write formal verification to prove the designs (when feasible). All designs will be written in SystemVerilog and will use SV simulations and SVA formal verification environments. You will run quality checkers (lint CDC RDC) and be expected to provide constraints and waivers when necessary. You will be asked to support the DV simulation team and the bring-up teams with the usage of new IP modules. All new designs are required to have documentation example code (where relevant) and integration notes. Expect to give presentations to cross-functional teams on the new IP designs.
- BS and a minimum of 10 years relevant industry experience
- Fluency in RTL design using SystemVerilog
- Experience designing for one or more AMBA protocols - AHB AXI APB
- Working knowledge of synthesis and static timing analysis
- Comfortable with clock domain crossings as well as CDC/RDC checking tools
- Fluency in SystemVerilog Assertions
- Background in low power design
- Understanding of embedded software design
- Experience in diagramming architectures and presenting designs to integration/software teams
Key Skills
- Aerospace Engineering
- Anti Money Laundering
- Electrical Installation
- Desktop Support
- Corporate Marketing
- Fabrication
About Company
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