In this role you will perform timing analysis on custom design circuits delivery timing views to integration teams as well as develop custom logic design in analog/mixed-signal circuits. You will work closely with custom design engineers and cross-functional teams at the silicon and module levels.
- BS and a minimum of 10 years relevant industry experience.
- Solid understanding of timing analysis concepts such as setup/hold time calculation POCV on timing paths timing constraints transistor-level delay characterization and rise/fall time balancing.
- Experience of timing analysis and verification in high-speed design such as SerDes and ADC.
- In-depth knowledge and analytical understanding of mixed-signal design techniques.
- Strong track record of delivering silicon IPs with design and verification.
- Proficiency in circuit modeling and simulation including SPICE models and worst-case corner selection.
- Experience with STA tools such as NanoTime PrimeTime and Tempus.
- Experience in analog/mixed-signal circuit design from architecture to fundamental implementation.
- Experience in SRAM design.
- Experience in timing / SDC constraints generation and management.
- Good understanding of tool algorithms for noise glitch cross-talk delay and margining with OCV / AOCVM / POCV.
- Proficiency in scripting languages (Python Tcl and Perl).
- Familiarity with synthesis logic equivalence DFT and backend related methodologies and tools.
- Strong communication and interpersonal skills.
In this role you will perform timing analysis on custom design circuits delivery timing views to integration teams as well as develop custom logic design in analog/mixed-signal circuits. You will work closely with custom design engineers and cross-functional teams at the silicon and module levels.BS...
In this role you will perform timing analysis on custom design circuits delivery timing views to integration teams as well as develop custom logic design in analog/mixed-signal circuits. You will work closely with custom design engineers and cross-functional teams at the silicon and module levels.
- BS and a minimum of 10 years relevant industry experience.
- Solid understanding of timing analysis concepts such as setup/hold time calculation POCV on timing paths timing constraints transistor-level delay characterization and rise/fall time balancing.
- Experience of timing analysis and verification in high-speed design such as SerDes and ADC.
- In-depth knowledge and analytical understanding of mixed-signal design techniques.
- Strong track record of delivering silicon IPs with design and verification.
- Proficiency in circuit modeling and simulation including SPICE models and worst-case corner selection.
- Experience with STA tools such as NanoTime PrimeTime and Tempus.
- Experience in analog/mixed-signal circuit design from architecture to fundamental implementation.
- Experience in SRAM design.
- Experience in timing / SDC constraints generation and management.
- Good understanding of tool algorithms for noise glitch cross-talk delay and margining with OCV / AOCVM / POCV.
- Proficiency in scripting languages (Python Tcl and Perl).
- Familiarity with synthesis logic equivalence DFT and backend related methodologies and tools.
- Strong communication and interpersonal skills.
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