FE Design and Timing Analysis Integration Engineer
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Job Location:
San Diego, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
28 days ago
Vacancies:
1 Vacancy
Job Summary
As a Front End and Timing Analysis Engineer you will be involved with all phases of implementing high performance low power wireless SoCs from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate chip or block level static timing constraints. Synthesize design with UPF/DFT/BIST. Close timing on critical blocks by working with design and PD teams. Perform timing optimization and implement the design for functionality. Generate and implement functional ECOs. Run static timing analysis flows at chip/block level and provide guidelines to fix violations to other designers. Participate in establishing/improving CAD and design flow methodologies. Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.
- Bachelors and 3 years of relevant industry experience.
- Knowledge of the ASIC design flow synthesis static timing analysis RTL to Post Synthesis netlist.
- Exposure to industry standard Timing Logic Equivalence Physical Design and Synthesis tools.
- Proficient in scripting in TCL Perl or Python.
- Hands-on experience in timing/SDC constraints generation analysis and management.
- Knowledge of timing corners operating conditions process variations and signal integrity-related issues.
- Understanding of UPF and low-power design and implementation techniques.
- Knowledge of basic SoC Architecture and HDL languages like Verilog to collaborate with our logic design team for timing fixes and functional ECOs.
Key Skills
- APIs
- Jenkins
- REST
- Python
- SOAP
- Systems Engineering
- Service-Oriented Architecture
- Java
- XML
- JSON
- Scripting
- Sftp
About Company
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