Senior Technical Staff Engineer Design for Test

San Jose, CA - USA

Monthly Salary: Not Disclosed

Posted on: 30+ days ago

Vacancies: 1 Vacancy

Job Summary

The DFT lead works in close partnership with different teams within the FPGA business unit spanning architecture ASIC design verification physical implementation and test engineering to implement the testability features into the combined FPGA and ASIC SOC. The DFT lead will be involved from the initial investigation and feasibility to tape-out as well as silicon validation and characterization of test methods on Automatic Test Equipment (ATE).

Responsibilities
(1.) Manage DFT requirements across architecture design and product teams to ensure coverage die cost test cost and DFT integration
requirements are met at the block and full chip level. Define implement and validate DFT features at the FPGA full chip and sub-systems
level.

(2.) Collaborate closely with cross functional teams to support DFT insertion synthesis scan insertion place-and-route static timing analysis timing closure power analysis during test and quantifying full chip test coverage.

(3.) Establish and maintain DFT design and insertion guidelines and documents best practices for all development teams to follow.

(4.) Be current with emerging technologies and methodologies in DFT and incorporate them into the FPGA to continuously improve test cost
and quality.

(5.) Work with Test and Product engineers to support development of firmware targeted test patterns ATPG and mBIST test feature validation processes and silicon debug activities.

(6.) Communicate project status and progress to chip lead and engineering management

Qualifications :

REQUIRED EXPERIENCE:
15 tears of DFT engineering experience through DFT pre and post silicon cycles

Experience in creating and implementing complex FPGA/SoC DFT architecture in advanced technology nodes

Expert level knowledge about IJTAG and JTAG test access Streaming Scan Network (SSN) scan compression and insertion SAF/TDF/PDF ATPG memory BIST and repair logic BIST MISRs at-speed testing of SoC/FPGA fault simulation quantifying full chip test coverage DFT mode timing constraints and power control during test.

Familiar with DFT verification silicon debug memory and scan diagnostics.

Experience in PHY high-speed IO digital communication and functional test development

Good understanding of Verilog synthesis physical implementation and STA

Good understanding of verification methodology

Preferred Skills and Experience:

Knowledge of FPGA design flow is a plus

Knowledge of embedded design and firmware methodology is a plus

Understanding Arm or RISC IPs high speed interfaces such as PAM4 SerDes DDR4/5 etc. is a plus.

Experience in leading multiple FPGA/SoC projects.

Additional Information :

Travel Time:

0% - 25%

Physical Attributes:

Feeling Handling Hearing Other Seeing Supervises Others Talking Works Alone Works Around Others

Physical Requirements:

10% walking 10% standing 80% sitting; 100% in doors; Usual business hours

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay restricted stock units and quarterly bonus addition to these components our package includes health benefits that begin day one retirement savings plans and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position which could be performed in California is $88000 - $232000.*

*Range is dependent on numerous factors including job location skills and experience.

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex gender identity sexual orientation race color religion national origin disability protected Veteran status age or any other characteristic protected by law.

Remote Work :

Employment Type :

Full-time