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Department Intro:
The DRAM Products Group (DPG) at Micron is dedicated to innovating and optimizing memory solutions. Our team designs and analyzes digital and analog circuits collaborating globally to deliver high-performance cost-effective and reliable DRAM products that meet the demands of modern computing. Layout Team Mission: Build precise high-quality reliable layouts on time every time while fostering development sharing knowledge and innovating as one team.
Role Summary:
As a Layout Engineer in DPG you will translate schematics into manufacturable layouts that meet design intent process rules and schedule commitments for advanced DRAM. Youll work closely with Design Process Integration and CAD teams to floorplan implement and verify custom digital memory and analog circuits and help us continuously improve methods automation and documentation so others can follow. You will play a crucial role in developing layouts for critical custom memory analog or standard cell circuits ensuring predictable ontime delivery of memory designs.
Responsibilities:
Design and Development: Create layout designs for critical circuits ensuring compliance with process rules and schematic intent. Work closely with Design Process and CAD engineers to deliver solutions from floorplan through final design.
Layout Verification: Perform verification tasks such as LVS (Layout vs. Schematic) DRC (Design Rule Check) and quality checks. Continuously improve verification tools and methodologies to ensure highquality layouts.
Methods Automation & Documentation: Tackle ambiguous problems; prototype solutions without a playbook; then codify them into guides/SOPs and share with the team. Contribute scripts (e.g. SKILL/Python) and layout method improvements to advance automation and drive measurable productivity gains. Integrate automated layout solutions to shape the future of layout design.
OnTime Delivery: Coordinate with global partners to meet predictable schedules and support tapeout/mask generation processes. Deliver blocklevel layouts within specified timelines while maintaining quality standards.
Project Management: Lead layout planning for assigned blocks or subprojects; coordinate priorities provide guidance to other engineers and ensure schedule alignment. Mentor team members on layout techniques verification best practices and tool usage.
Minimum Qualifications:
Bachelors in Electrical/Computer Engineering (or related).
Proficiency in layout tools and methodologies including Cadence Virtuoso VXL and Calibre for DRC/LVS/Verifications.
2 years of semiconductor custom/memory/analog layout experience.
Solid understanding of CMOS processes design rules and layoutdependent effects.
Proven problemsolving in ambiguity with high attention to detail and quality.
Preferred Qualifications:
8 years of semiconductor custom/memory/analog layout experience with demonstrated block/project leadership including mentoring and schedule management.
DRAM/LPDDR/HBM memory product layout background; familiarity with tapeout/mask generation flows.
Scripting (SKILL Python) and experience building methodology/automation.
Strong collaboration skills across global crossfunctional teams; excellent written documentation abilities.
As a world leader in the semiconductor industry Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well provide peace of mind and help you prepare for the future. We offer a choice of medical dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury and paid family leave. Additionally Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available please see the Benefits Guide posted on is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race color religion sex sexual orientation age national origin citizenship status disability protected veteran status gender identity or any other factor protected by applicable federal state or local laws.
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Required Experience:
Staff IC
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