Senior Applications Engineer – DDR Design IP
Share
Job Location:
San Jose, CA - USA
Monthly Salary:
$ 84000 - 156000
Posted on:
30+ days ago
Vacancies:
1 Vacancy
Job Summary
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
Senior Applications Engineer DDR Design IP
Job Location: San Jose CA
Job Description
The Cadence IP team develops industry leading IPs that enable customers in a variety of markets - from the endpoint to the edge to the cloud. At Cadence were helping set the standard on IP products that get integrated in SoCs that power the worlds Data Centers Automobiles Cloud and Wireless Systems. We offer amazing opportunities to grow in your career.
We are growing our Memory IP presales team and we are looking for smart energetic collaborative and creative people to help us lead the industry with our IP products. At Cadence we believe in embracing diverse ideas and striving for excellence in all that we do. Do you want to make a difference and be challenged Join the High-Performance Culture at Cadence.
As a Technical Presales Engineer you will support the technical presales of DDR IP by generating collateral through simulations synthesis and publications. As you grow into more senior roles you will use your knowledge of different memory interface standards to architect memory solutions for customers using Cadence DDR IP. This role offers the benefit of both technical growth and business skill development. You will be part of the Technical Field Organization helping educate customers and providing solutions using our DDR IP portfolio. Our memory PHY and controller IPs are used in data centers mobile devices automobiles and consumer devices.
Responsibilities include:
Technical presales of Memory IP
Gain expertise in memory controller and PHY IPs and DDR protocols
Work closely with IP Sales staff marketing and R&D teams to win opportunities
Run Verilog simulations to enable IP benchmarking
Run RTL synthesis for area and timing analysis
Present IP demos to customers
Travel to customer sites may be required occasionally
Qualifications:
BS/MS in EE CE or related majors
Knowledge of Computer Architecture and Electronics circuits
Knowledge of Verilog HDL
Experience with simulation and synthesis tools
Excellent presentation skills and verbal/written communication skills is a must
Nice to have:
Familiarity with one or more DRAM protocols DDR4/5 LPDDR4/5/5X HBM2/3 GDDR6
Perl/Python Scripts
Experience on memory subsystem verification and/or performance analysis
Strong knowledge of ASIC flow RTL design in Verilog System Verilog and FPGA design
Knowledge of AXI DFI protocols
Working knowledge of memory controller and memory PHY
The annual salary range for California is $84000 to $156000. You may also be eligible to receive incentive compensation: bonus equity and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications skill level competencies and work location. Our benefits programs include: paid vacation and paid holidays 401(k) plan with employer match employee stock purchase plan a variety of medical dental and vision plan options and more.
Were doing work that matters. Help us solve what others cant.
Required Experience:
Senior IC
Key Skills
- Dhcp
- Active Directory
- VMware
- ASA
- Solarwinds
- Access Points
- F5
- Load Balancers
- QoS
- Nexus
- Routers
- Windows
- Visio
- Hsrp
- Dns
About Company
Do you want to shape the future of technology? Cadence is leading the charge to solve some of technology’s toughest challenges. We work with the world’s most innovative companies, across a growing range of industries. Major trends that you hear about everyday – like artificial intell ... View more
