SoC Design Lead

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

The role sits within the Custom Compute & Storage (CCS) business unit which develops high-performance silicon platforms for AI cloud carrier and enterprise markets. The CCS HW org is distributed across global sites and is focused on delivering scalable low-power and high-performance SoCs.

This is a strategic position that ideally will reside in Santa Clara.

What You Can Expect

As aSoC Design Lead you will be responsible for driving the technical execution of complex SoC programs from architecture through tape-out ensuring cross-functional alignment and design excellence. Your responsibilities will span across multiple domains and phases of development:

Architecture & Specification

• Collaborate with systems and architecture teams to define SoC-level specifications including performance power area and feature requirements
• Translate high-level product requirements into detailed micro-architecture specifications for subsystems and IP blocks

RTL Design & Integration

• Lead RTL development and integration efforts ensuring modularity reusability and compliance with design guidelines
• Own the top-level SoC integration including clocking resets interconnects (AXI AHB APB) and host interfaces (PCIe CXL)

Verification & Emulation

• Partner with DV leads to define and review verification plans including functional coverage-driven and power-aware verification
• Oversee emulation strategy and ensure emulation-friendly RTL is delivered for early validation
• Support pre-silicon validation and emulation bring-up including FPGA prototyping and lab debug

Post-Silicon Validation

• Lead post-silicon debug efforts working closely with lab teams to resolve complex issues and validate performance targets
• Ensure readiness for silicon bring-up including test plans debug hooks and validation infrastructure

Physical Design & DFT Coordination

• Interface with physical design and DFT teams to ensure seamless handoff and integration of RTL into backend flows
• Review synthesis STA and DFT insertion results to ensure timing closure and testability goals are met

Process & Flow Compliance

• Ensure adherence to internal design processes and milestone reviews including design maturity assessments and quality metrics
• Drive standardization of tools flows and methodologies across projects to improve productivity and efficiency

Cross-Functional Collaboration

• Coordinate with firmware software and system validation teams to ensure holistic SoC functionality and performance
• Collaborate across global sites and time zones to align execution and resolve dependencies

Leadership & Mentorship

• Provide technical guidance and mentorship to junior engineers and cross-functional peers
• Foster a culture of ownership innovation and continuous improvement within the design team

Program Execution & Reporting

• Track design progress identify risks and drive mitigation plans to ensure schedule adherence
• Present status updates and technical reviews to senior leadership and stakeholders

What Were Looking For

• Bachelors or Masters degree in Electrical Engineering Computer Engineering or related field.
• 15 years of experience in SoC development including RTL development integration architecture verification and implementation.
• Deep understanding of interconnects (AXI AHB APB) memory controllers (DDR/LPDDR/HBM) and host interfaces (PCIe CXL).
• Experience with multi-die integration power management and thermal challenges.
• Strong leadership and cross-functional collaboration skills.
• Familiarity with design tools and flows: lint CDC synthesis timing closure etc.

Expected Base Pay Range (USD)

194290 - 291000 $ per annum

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell we offer a total compensation package with a base bonus and and financial wellbeing are part of the package. That means flexible time off 401k plus a year-end shutdown floating holidays paid time off to volunteer. Have a question about our benefits packages - health or financial Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.

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