You will be responsible to deliver a fully-verified clean layout. This would include the following: - Designing sophisticated layouts for mixed signal and analog circuits in deep sub-micron CMOS technologies. - Reviewing and analyzing floorplans and complex circuits with circuit designers. - Running a complete set of design verification tools available on AMS blocks. - Working with the circuit design team to plan/schedule work and negotiate any necessary layout tradeoffs as needed. - Interpreting LVS DRC and ERC reports to find the fastest way to complete the layout. - Exceeding engineering specifications and expectations by working closely with the design team. - Applying advanced CAD tools and mask design knowledge to deliver an accurate and robust layout that meets stringent matching performance area and power requirements.
- Typically requires more than 5 years of experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits.
- Experience implementing analog layouts to achieve tight matching low noise and low power consumption. Layouts may include analog blocks resistors capacitors IO pads ESD structures etc.
- Solid understanding of layout techniques for handling IR drop RC delay electro-migration and coupling capacitance.
- Understanding of guard-rings DNW PN junctions and LDE (Layout Dependent Effect) and proactively work with circuit designers to identify the best approach.
- High-level proficiency in interpretation of Calibre DRC LVS ERC etc. reports.
- Familiar with Layout CAD tools like Siemens Calibre and Cadence Virtuoso.
- Excellent communication and interpersonal skills and able to work with multi-functional teams.
- Analog/mixed-signal layout design experience in CMOS high-voltage process.
- Scripting skills in PERL or SKILL are a plus.
- E-mail and verbal communication in English are considered a plus.
You will be responsible to deliver a fully-verified clean layout. This would include the following: - Designing sophisticated layouts for mixed signal and analog circuits in deep sub-micron CMOS technologies. - Reviewing and analyzing floorplans and complex circuits with circuit designers. - Running...
You will be responsible to deliver a fully-verified clean layout. This would include the following: - Designing sophisticated layouts for mixed signal and analog circuits in deep sub-micron CMOS technologies. - Reviewing and analyzing floorplans and complex circuits with circuit designers. - Running a complete set of design verification tools available on AMS blocks. - Working with the circuit design team to plan/schedule work and negotiate any necessary layout tradeoffs as needed. - Interpreting LVS DRC and ERC reports to find the fastest way to complete the layout. - Exceeding engineering specifications and expectations by working closely with the design team. - Applying advanced CAD tools and mask design knowledge to deliver an accurate and robust layout that meets stringent matching performance area and power requirements.
- Typically requires more than 5 years of experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits.
- Experience implementing analog layouts to achieve tight matching low noise and low power consumption. Layouts may include analog blocks resistors capacitors IO pads ESD structures etc.
- Solid understanding of layout techniques for handling IR drop RC delay electro-migration and coupling capacitance.
- Understanding of guard-rings DNW PN junctions and LDE (Layout Dependent Effect) and proactively work with circuit designers to identify the best approach.
- High-level proficiency in interpretation of Calibre DRC LVS ERC etc. reports.
- Familiar with Layout CAD tools like Siemens Calibre and Cadence Virtuoso.
- Excellent communication and interpersonal skills and able to work with multi-functional teams.
- Analog/mixed-signal layout design experience in CMOS high-voltage process.
- Scripting skills in PERL or SKILL are a plus.
- E-mail and verbal communication in English are considered a plus.
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