Analog IC Design Engineer, Senior Staff

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

You will be working with multi-functional teams to deliver high-speed transceiver products. You will define specifications based on link budget behavioral modeling and transistor-level feasibility. You will also drive schematic design and collaborate on mask design for implementation. And finally with the team you will drive designs into volume production and delight customers.

What Were Looking For

• Bachelors degree in Electrical Engineering or related fields and 5-10 years of related professional experience.
• Masters degree and/or PhD in Electrical Engineering or related fields and 3-5 years of experience.
• The ideal candidate will have a deep understanding of analog mixed-signal design with experience in high-speed transceivers.
• Solid understanding and experience of designing analog mixed-signal circuit blocks including PLL phase interpolator low jitter clock distribution bandgap biasing circuits LDO regulators amplifiers comparators high-speed DACs and ADCs filters.
• In-depth knowledge of analog mixed-signal concepts like mismatch mitigation linearity stability low-power and low-noise techniques.
• Hands-on experience with AMS IC development from definition to high-volume production including layout supervision bench evaluation correlation and characterization.

EXPERIENCE IN THE FOLLOWING AREAS IS DESIRABLE:

• Experience in lab testing of high-speed transceivers.
• Modeling of passive on-chip elements such as inductor T-coil and transformer.
• Able to build VerilogA/AMS behavioral models.
• Able to analyze and lead characterization data from lab and volume testing
• Knowledge of ESD requirements.

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.