Analog SERDES Architect

San Jose, CA - USA

Monthly Salary: Not Disclosed

Posted on: 30+ days ago

Vacancies: 1 Vacancy

Job Summary

JOB DESCRIPTION

Role: Analog SERDES Architect
Location: San JoseCA (onsite)
Duration: Full time

Note- Experience level- 6 Years

Role Description
We are looking for an Analog SERDES Architect with 6 years of hands-on experience in high-speed IO circuit design. The candidate will define and architect analog front-end building blocks for SERDES PHYs at cutting-edge technology nodes. Youll play a key role in developing power-efficient high-performance SERDES solutions for applications like PCIe CXL UCIe and Ethernet.

Key Responsibilities

Architect and design analog/mixed-signal circuits (TX RX PLL CDR Equalizers Drivers).
Perform feasibility analysis trade-off studies and power/performance optimization.
Conduct transistor-level simulations corner analysis and modeling.
Work closely with system and digital teams for co-optimization.
Lead design reviews and contribute to layout and post-layout verification.
Support post-silicon bring-up validation and debug of SERDES IP.

Qualifications

6 years of hands-on analog design in SERDES/High-Speed IO.
Strong expertise in PLL/CDR design equalization techniques and TX/RX circuits.
Proficiency with SPICE Spectre and other analog design tools.
Understanding of signal integrity jitter channel modeling and packaging.
MS/PhD in Electrical Engineering or equivalent (preferred).

JOB DESCRIPTION Role: Analog SERDES Architect Location: San JoseCA (onsite) Duration: Full time Note- Experience level- 6 Years Role Description We are looking for an Analog SERDES Architect with 6 years of hands-on experience in high-speed IO circuit design. The candidate will define and arch...