SOC Verification Engineer
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Job Location:
San Francisco, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
30+ days ago
Vacancies:
1 Vacancy
Job Summary
Understand details of microarchitecture and build block / chip level testbench using best-in-class verification verification plan from specification and in coordination with directed and ingenuous constrained random coverage model and enhance testbench/test to increase automated flows for block and chip level failures manage bug tracking and close detailed verification reviews and set standard for coding closely with team members to improve methodology and flow.
- Solid fundamentals in Verilog and SystemVerilog for verification.
- Basic knowledge of UVM methodology.
- Solid verification skills in problem solving and debugging.
- Experience with Constrained Random testing is a plus.
- Good understanding of overall verification flow
- Knowledge of industry standard interfaces like I2C UART SPI.
- Understanding and usage of System Verilog Assertion (SVA)
- Programing experience in C
- Experience writing scripts in languages such as Perl or Python a plus.
- Should be a great teammate with excellent communication skills and the desire to take on diverse challenges.
- Typically requires MSEE with 0-3 years of experience
Key Skills
- Account Management
- Apache Web Server
- Jpa
- ABAP
- Community Support
- Islamic Banking
About Company
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