SOC Verification Engineer
SOC Verification Engineer
Employer Active
Job Alert
You will be updated with latest job alerts via email
Share
Job Alert
You will be updated with latest job alerts via email
Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
- Solid fundamentals in Verilog and SystemVerilog for verification.
- Basic knowledge of UVM methodology.
- Solid verification skills in problem solving and debugging.
- Experience with Constrained Random testing is a plus.
- Good understanding of overall verification flow
- Knowledge of industry standard interfaces like I2C UART SPI.
- Understanding and usage of System Verilog Assertion (SVA)
- Programing experience in C
- Experience writing scripts in languages such as Perl or Python a plus.
- Should be a great teammate with excellent communication skills and the desire to take on diverse challenges.
- Typically requires MSEE with 0-3 years of experience
Employment Type
Full-Time
