DV Engineer

Sunnyvale, CA - USA

Monthly Salary: Not Disclosed

Posted on: 30+ days ago

Vacancies: 1 Vacancy

Job Summary

Job Description
Role: DV Engineer
Work Location: Bay Area CA
Position Type: 12 months

Required qualifications:

3 years of hands-on experience in Verilog SystemVerilog C/C based verification and UVM methodology.
3 years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.
Experience in one or more of the following areas along with functional verification - SV Assertions Formal Emulation.
Experience in EDA tools and scripting (Python TCL Perl Shell) used to build tools and flows for verification environments.
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.

Preferred Qualifications

Experience in development of UVM based verification environments from scratch.
Experience with Design verification of Data-center applications like Video AI/ML and Networking designs.
Experience with revision control systems like Mercurial(Hg) Git or SVN.
Experience with low power design.

Job Description Role: DV Engineer Work Location: Bay Area CA Position Type: 12 months Required qualifications: 3 years of hands-on experience in Verilog SystemVerilog C/C based verification and UVM methodology. 3 years experience in IP/sub-system and/or SoC level verification based on SystemVer...