With mentorship you will work within the Digital Design Team to refine or create requirements and specifications collaborate with the analog design and design verification teams create/update RTL designs and run simulations to check your design. This could include tasks such as implementing bespoke control of analog circuits creating state machines to control the system or working on industry standard interfaces to high performance SoCs. Your designs will need to balance energy efficiency and area constraints with project schedule and maintainability. You may also review synthesis and power reports root-cause and resolve timing and power issues and ensure maximal QoR throughout your design.
- Enrolled in Bachelors/Masters/PhD studies in EE or related field
- Excellent interpersonal skills and well-organised working style
- Fluent English skills are required
- Availability for at least 6 months
- Coursework focusing on modern energy-efficient/low-power logic design techniques
- Strong familiarity with RTL design in Verilog/VHDL and understanding of the logic structures being inferred
- Ability to work well in a team and be productive under tight schedules
- Strong analytical/problem solving skills
- An understanding of finite state machines CPU bus architectures and mixed signal design
Required Experience:
Intern
With mentorship you will work within the Digital Design Team to refine or create requirements and specifications collaborate with the analog design and design verification teams create/update RTL designs and run simulations to check your design. This could include tasks such as implementing bespoke ...
With mentorship you will work within the Digital Design Team to refine or create requirements and specifications collaborate with the analog design and design verification teams create/update RTL designs and run simulations to check your design. This could include tasks such as implementing bespoke control of analog circuits creating state machines to control the system or working on industry standard interfaces to high performance SoCs. Your designs will need to balance energy efficiency and area constraints with project schedule and maintainability. You may also review synthesis and power reports root-cause and resolve timing and power issues and ensure maximal QoR throughout your design.
- Enrolled in Bachelors/Masters/PhD studies in EE or related field
- Excellent interpersonal skills and well-organised working style
- Fluent English skills are required
- Availability for at least 6 months
- Coursework focusing on modern energy-efficient/low-power logic design techniques
- Strong familiarity with RTL design in Verilog/VHDL and understanding of the logic structures being inferred
- Ability to work well in a team and be productive under tight schedules
- Strong analytical/problem solving skills
- An understanding of finite state machines CPU bus architectures and mixed signal design
Required Experience:
Intern
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