RTL Design Engineering Internship

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the worlds most highly integrated SoCs Silicon Labs provides device makers the solutions support and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin Texas Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home industrial IoT and smart cities markets. Learn more at.

Our Engineers solve real-world problems within a highly collaborative team of the industrys most innovative talent. As a Silicon Labs Intern you will help create and extend our offering of wireless solutions for smart cities. We count among our customers some of the most recognized and well-respected companies in the world and innovators in IoT.

You will be part of a highly skilled and tight-knit team where everyone has a significant impact on and responsibility for the end product.

The Rennes site is cross-functional and therefore youll be part or interacting firsthand with chip and embedded software designers or customer application team. Silicon Labs is a global company and youll have regular interactions with our extended teams across the world. We strive to strike a good work/life balance and make our environment welcoming and fun so we seek someone whose technical skills are matched by their interpersonal skills.

What Youll Do

Projects are specifically tailored to each intern ensuring a meaningful contribution to both your skillset and Silicon Labs.

Within our DSP design team in charge of studying new modem algorithms and architecture anticipating future needs you will study possibilities offered by different kind of channel coding schemes.

In IOT standards we see emerging needs of transmission for long-range / low data-rate small packets with strong and efficient encoding.

Based on an existing RTL code for a Front-End (FE) filtering block you will make the necessary adaptations of the specifications to suit a new application and analyze possible optimizations.

Using the above FE block as a reference implementation you will study the feasibility of using GenAI tools for RTL code analysis (find bugs propose optimizations) and generation (propose a new implementation).

You will evaluate the capability as well of GenAI for testbench generation and verification of a block.

If time allows it you will also develop (with assistance from GenAI) the RTL code for a small NPU (Neural Processing Unit) that will be used to implement a Signal Processing task (e.g. preamble detection) using Machine Learning techniques.

Your tasks will spread over different subjects function of your expectation our needs and evolution of the project:

• Analyze and develop RTL code unassisted at first and then with the help of GenAI tools

• Simulate in Matlab the performance of the FE and compare with RTL implementation

• Assess performance vs area tradeoffs in state-of-the-art systems developed by Silicon Labs for future products

• Assist in evaluating the feasibility of Machine Learning techniques for Signal Processing (focus on RTL implementation)

Who You Are

You are an innovator builder and tinkerer. You have a curious mind and a drive to succeed. You want to work with a global team of technology enthusiasts and design pioneers. Heres what you need:

• You are in the last year of a Masters degree in computer science computer engineering electrical engineering electronics or similar

• You have some combination of the following skills:

  • RTL Design: Verilog System Verilog VHDL

  • Digital Design: Signal processing (filtering FIR IIR etc.) Digital Communications

• Software: Matlab Python Embedded C Scripting

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race religion color national origin gender sexual orientation age marital status veteran status or disability status or any other characteristic protected by applicable law.