You will work jointly with designers and architects to understand various functional blocks and their use-cases. Write debug and integrate new tests for integrated Wireless chipsets complex Digital Interfaces and Power Management Subsystems. We push functional blocks to their limits and debug issues surfaced during testing. Work with other groups and organizations to push these tests down into pre-silicon environments. We work closely with hardware design engineers to debug silicon issues exposed during testing. Support product development builds locally and remotely.
BS and a minimum of 3 years relevant industry experience
MSEE Preferred
Strong understanding of SoC/FPGA architecture and silicon micro-architecture
Experience in writing basic embedded software routines and test scripts
Experience with hardware/software interaction
Solid Digital logic fundamentals including timing analysis state-machine debug and/or RTL/test-bench development Experience with high-speed memory systems and communication interfaces
Good understanding of MAC Protocol specifications for digital interfaces
Experience in crafting tests to target specific portions of silicon designs and digital interconnects
Hands on debug experience with usage of modern lab equipment (DSOs Logic Analyzers Protocol Analyzers)
Familiarity with interpreting and navigating schematics and layout
Strong desire to deep-dive system level issues and drive problems to closure in a team-based environment with a proactive demeanor
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