Senior Staff Digital Design Engineer – Wireline PHYs

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

• Architect and implement RTL for digital control DSP blocks digital datapath and adaptation engines of PHY IP targeting SerDes Die-to-Die and Parallel Optics applications.
• Design and verify bus interfaces (APB AHB AXI) and register maps for microcontroller communication and firmware control.
• Collaborate closely with system architects and firmware teams to optimize PHY integration into SoC and chiplet environments.
• Drive timing closure and ensure synthesis-friendly RTL targeting system-level constraints and goals including DSP and datapath optimizations.
• Support system bring-up activities validation planning and post-silicon debug with a focus on system-level interactions involving digital datapath and DSP logic.
• Mentor junior engineers and contribute to improving design methodologies for PHY system integration including DSP and datapath design best practices.
  

What Were Looking For

• Masters degree 7 years or PhD 4 years in Electrical Engineering Computer Engineering or related fields.
• Strong RTL design expertise in Verilog/SystemVerilog with a focus on digital control blocks DSP digital datapath and bus protocols.
• Solid understanding of logic synthesis static timing analysis (STA) constraints development and timing closure at block and chip levels.
• Deep knowledge of CDC and RDC design principles.
• Experience integrating PHY digital blocks including DSP and datapath modules with embedded microcontrollers including interrupt and event handling.
• Familiarity with scripting for design automation (Python TCL Perl).
• Proven problem-solving and debug experience at system level including post-silicon validation particularly for DSP and datapath components.
• Preferred: understanding of firmware-hardware co-design and system bring-up tools.

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.