2026 Intern SoC RTL Design and Integration
2026 Intern SoC RTL Design and Integration
Posted on :
27-08-2025
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1 Vacancy
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Job Description
Responsibilities
- Work on SOC Front-end design team be responsible for the SOC subsystem design including subsystem integration RTL coding design rule check and constrain delivery.
Requirements:
- Strong Verilog and C coding skills
- Knowledge of on-chip bus protocols: AMBA AXI or similar is a plus
- Extensive knowledge and experience in front-end implementation tasks such as constraint definition (timing & power) synthesis power analysis equivalence checking and STA is a plus
- Good English communication skills.
Required Experience:
Intern
Employment Type
Part-Time
Key Skills
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