Adv Packaging Principal Yield Engineer

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Summary of Role: The ULP CMOS product team is looking to hire a yield engineer to join our growing Advanced packaging team in our Singapore facility. Applicants for this position would be responsible for monitoring yield health of the development programs in the advanced packaging new features and new offerings on base technologies in FINFET and FDSOI from early process demonstration through manufacturing transfer. Areas of focus could include monitoring in-line inspection measurements and electrical performance of the features we are developing for the advanced packaging support of the full ULP CMOS suite of products.

Essential Responsibilities:

• The advanced packaging yield will drive yield and product enhancement for technology nodes across the ULP CMOS product lines for multiple development opportunities.

• This role supports advanced packaging yield learning and requires strong partnership and collaboration with the broader SGP module engineering team and process integration to report signals and reports of health of these programs.

• Investigate root cause of yield and product functionality issues. Use electrical data analysis failure isolation product and design information device knowledge and technology understanding to identify solutions. Include learning from test chips and test structures for yield limiter determination and improvement.

• Integrate physical and electrical data to establish yield/ defectivity paretos and roadmaps.

• Work with internal and external test and assembly sites to maximize electrical feedback to the factory.

• Develop and improve yield characterization and data analysis methodologies to determine yield limiters correlation to in-line defectivity and electrical parametric signals.

• Support process module engineering activities to improve cost cycle time and manufacturing readiness.

• Ensure methods and processes in place to test the devices and structures being developed

• Analyze various data physical electrical or defect reports to determine trends and recommend corrective actions

• May require creation of presentations to provide occasional management or external customer updates.

• Work and collaborate other projects and/or assignments as needed

Other Responsibilities:

• Perform all activities in a safe and responsible manner and support all Environmental Health Safety & Security requirements and programs

• Travel <10% to other GlobalFoundries facilities may be necessary

Required Qualifications:

• Bachelors Degree in Circuit Design Electrical Engineering or related technical field

• Minimum of 5 years of semiconductor product yield or test engineering circuit design process integration or process engineering experience

• Strong candidates will have demonstrated experience in yield analysis techniques and methodologies solid understanding of electrical parametric correlation to product yield and good knowledge of semiconductor processing and process integration.

• Excellent verbal and written communication skills.

• Strong interpersonal skills and ability to work effectively within a global matrixed team or environment.

• Prior experience in transferring implementing ramping and sustaining process technologies in early development through manufacturing ramp into production

• Strong fundamental understanding of circuit design and test solid state device physics submicron FET architecture and the implications of electrical characteristics and performance on yield and product behavior.

• Candidates must have capabilities in the design execution and analysis of experiments. - Proven project management peer leadership and mentoring skills. Preferred Qualifications: - Experience in advanced technology (45nm node or below) is strongly preferred.

• Experience in digital CMOS or analog circuit or test structure design characterization test/debug yield enhancement and/or product engineering.

• Fluency in English Language written & verbal

Preferred Qualifications:

• M.S. or Ph.D. preferred

• Experience in advanced packaging technology (45nm node or below) is strongly preferred.

• Experience with contract / external test and assembly sites a definite bonus.

• Experience in digital CMOS or analog circuit or test structure design characterization test/debug yield enhancement and/or product engineering.

GlobalFoundries is an equal opportunity employer cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity efficiency and innovation whilst our employees feel truly respected valued and heard.

As an affirmative employer all qualified applicants are considered for employment regardless of age ethnicity marital status citizenship race religion political affiliation gender sexual orientation and medical and/or physical abilities.

All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks medical screenings as applicable and subject to the respective local laws and regulations.