At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
Key Responsibilities:
Execute System-Level Verification: Develop and run test plans for ARM-based SoCs using UVM methodology focusing on subsystem and SoC-level interactions.
Performance Testing: Create scenarios to analyze system performance (latency throughput bandwidth) collect metrics and collaborate with architects to identify bottlenecks.
Testbench Development: Contribute to building and maintaining modular UVM testbenches for system-level features interconnect traffic and power sequences.
Scenario-Based Testing: Simulate real-world use cases involving multi-core operations memory traffic (AMBA) and boot sequences.
Required Skills & Qualifications:
Bachelors/Masters in Electrical/Computer Engineering or related field.
3-5 years of hands-on ASIC/SoC verification experience.
UVM Proficiency: Demonstrated experience developing UVM testbenches and test sequences.
AMBA Knowledge: Working experience with AMBA protocols (AXI AHB APB)
ARM Exposure: Understanding of ARM SoC architectures (Cortex-A/M/R cores memory subsystems).
System Verification: Experience verifying IP/sub-system interactions within an SoC context.
Performance Awareness: Ability to develop performance tests and interpret simulation metrics.
Debug Skills: Competence in debugging testbench/RTL failures using waveforms/logs.
Technical Skills: Proficient in SystemVerilog and scripting (Python/Perl/Tcl).
Tool Experience: Exposure to industry simulators (VCS Xcelium or Questa).
Preferred Skills:
Exposure to multi-core/coherency protocols (e.g. ACE/CHI).
Familiarity with C/C for test stimulus or firmware interaction.
Basic understanding of low-power verification concepts (UPF/CPF).
Awareness of high-speed interfaces (PCIe USB DDR).
Interest in performance modeling or emulation (Palladium/Zebu/HAPS).
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