Senior StaffStaff Design Verification Engineer
Senior StaffStaff Design Verification Engineer
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Job Description
Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the worlds most highly integrated SoCs Silicon Labs provides device makers the solutions support and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin Texas Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home industrial IoT and smart cities markets. Learn more at.
Meet the Team
The IoT Digital team is a state-of-art IC design team focused on producing world-class Wireless MCU SoCs. The architecture specification design verification and implementation of the Wireless MCU SoCs is the responsibility of the IoT Digital team. These SoCs include an embedded CPU system with analog and digital peripherals advanced security state-of-the-art power management and best-in-class radios to support a wide range of wireless IoT applications and standards.
As aDesign Verification Engineer you will be responsible for ensuring the correctness and functionality of complex digital designs particularly those involving analog and mixed-signal components. Your expertise in cosimulation will play a crucial role in verifying interactions between digital and analog blocks. Below are the key responsibilities and qualifications for this role:
Duties & Responsibilities:
Digital AMS Cosimulation:
Develop and maintain acosimulation environmentthat allows seamless verification between digital RTL (Register Transfer Level) modules and analog/mixed-signal models (SV Verilog A VAMS C/C) or spices netlist.
Verify interactions data exchange and communication between these different representations of the design.
Testbench Development:
CreateSystem Verilog-based VMM/UVM test benchesfor digital components.
Specify testbench requirements and coverage plans.
Implement constrained-random sequences agents and environments using UVM.
Complex Verification Environments:
Build and maintaincomplex and reusable verification environmentsusing methodologies such as UVM and SystemVerilog (SV).
Write comprehensivetest plansand create test benches to execute those plans.
Analyze coverage metrics identify and address test bench gaps and run regressions.
File bug reports as needed.
Qualifications:
Education: A relevant degree such as a Masters or Bachelors Degree in Computer Science Electrical Engineering Computer Engineering or related fields.
Skills:
Proficiency inSystem Verilog Assertion-based Formal Verificationand UVM.
Familiarity withVerilogVerilog A C and TCL
Knowledge of industry-standard interfaces.
Tools proficiency in Xcelium Spectre Questasim Symphony
Scripting skills in languages likePythonorPerl is a plus
Experience:
Ideally 10-15 years of industry experience.
Benefits & Perks:
You can look forward to the following benefits:
Employee Stock Purchase Plan (ESPP)
Insurance plans with Outpatient cover
Flexible work policy
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Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race religion color national origin gender sexual orientation age marital status veteran status or disability status or any other characteristic protected by applicable law.
Required Experience:
Staff IC
Employment Type
Full-Time
