In this job you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits with embedded micro-controller advanced DFT architectures and very low power design requirements. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing RTL assertions debugging code and otherwise interacting with the design verification team. Additionally you will be responsible for various front end methodology flows that include pre-silicon power analysis clock domain crossing reset domain crossing and unified power flow UPF). You will participate in the lab bring-up of those circuits by potentially writing test scripts analyzing lab data proposing experiments etc.
BS degree in technical discipline with minimum 10 years of relevant experience.
Deep knowledge of mixed signal concepts
Deep knowledge of RTL design fundamentals (control and data path).
Deep knowledge of Verilog and SystemVerilog.
Deep knowledge of front-end tools (Verilog simulators linters clock-domain crossing checkers reset domain crossing unified power flow logic equivalence checkers).
Working knowledge of synthesis static timing and DFT (scan analog/digital functional/production test).
Deep knowledge of System-Verilog assertions checkers and other design verification techniques.
Deep knowledge of scripting languages. Perl and Python are plusses.
Disclaimer: Drjobpro.com is only a platform that connects job seekers and employers. Applicants are advised to conduct their own independent research into the credentials of the prospective employer.We always make certain that our clients do not endorse any request for money payments, thus we advise against sharing any personal or bank-related information with any third party. If you suspect fraud or malpractice, please contact us via contact us page.