Cellular PPAC (Power, Performance Area and Cost) Engineer
Cellular PPAC (Power, Performance Area and Cost) Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
- Minimum BS and 10 years of relevant industry experience.
- VLSI background with hands-on experience in RTL to GDSII flows.
- Prior experience in doing Power Performance Area and Cost optimizations for SoCs.
- Experience with SoC power flows & Vmin optimization.
- Experience with Design Technology Co-optimization identifying and solving scaling bottlenecks in new technology nodes.
- Rapid prototyping and scripting of methodologies and test chip block implementation.
- Solid understanding of Physical Design challenges proficiency with synthesis place and route tools and implementation exploration.
- Experience with Metal stack optimizations.
- Experience performing Early Tech node analysis to identify implementation bottlenecks.
- Design Technology Co-optimization expertise.
- Strong analytical skills and ability to identify and communicate high return on investment opportunities.
- Ability to apply data science and ML analytics for Frontend and Backend databases as well as post-silicon data to identify trends & patterns and fine-tune implementation methodologies.
Employment Type
Full Time
