Master thesis in Performance Improvement of a RISC-V Core for DSP Applications
Master thesis in Performance Improvement of a RISC-V Core for DSP Applications
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Salary Not Disclosed
1 Vacancy
Job Description
- During your assignment you will improve RISC-V Core Performance for FFT and FIR (HW Implementation).
- The implementation of a DSP Algorithm from an automotive application is your task.
- You will evaluate the DSP algorithms performance on RISC-V compared to an internal DSP core.
- Furthermore you will analyse instructions contributing to the performance of running the DSP algorithm on the RISC-V core.
- Last but not least you will improve the RISC-V core for running the automotive DSP algorithm.
Qualifications :
- Education: Master studies in the field of Electrical Engineering or Computer Science
- Experience and Knowledge: on microprocessor architecture digital hardware implementation Verilog or VHDL
- Personality and Working Practice: a do-it-yourself character who is communicative and enthusiastic
- Work Routine: office preferred
- Languages: business fluent in German and very good in English
Additional Information :
Start: according to prior agreement
Duration: 6 months
Requirement for this thesis is the enrollment at university. Please attach your CV transcript of records examination regulations and if indicated a valid work and residence permit.
Diversity and inclusion are not just trends for us but are firmly anchored in our corporate culture. Therefore we welcome all applications regardless of gender age disability religion ethnic origin or sexual identity.
Need further information about the job
Atefe Dalirsani (Functional Department)
#LI-DNI
Remote Work :
No
Employment Type :
Full-time
Employment Type
Full-time
