You will drive requirements and execution of products process and package qualification and reliability stress tests conditions and configurations from design stage all the way to successful qualification and review Design for Reliability and Design for Test to ensure stress-ability and all aspects of and ensure adequate preparation for qualification including such as corner skew material BIB/Socket waveform electrical bias thermal effect lifetime POR of process flows workmanship standards and supervise product FAI (First Article Inspection) to ensure critical goals are reviewed before engineering pre-production and production release for Product investigation and resolution on qualification fallouts and product and process nonconformance of MRB RMA events through means of FA CAR 8D and PCN or ECN supplier audits when needed. Assess/perform yield analysis and correlation analysis for all levels of test including Pareto building statistics etc. Drive/guide suppliers for improvement as needed.
BS degree and 10 years of industry experience.
Experience in JEDEC reliability and quality related standards ISO and the science behind them.
Travel is required for this role.
You will have 15 years of semiconductor engineering in the Reliability and/or Quality/Product Engineering role from multinational companies.
Experience with silicon product level reliability qualification and lifetime behavior model.
Prior experience defining hardware setups and equipment for life environmental ESD Latch-Up and other tests.
Validated auditing of supplier sites materials and processes.
Experience driving suppliers in the areas of silicon Fab process / packaging / assembly test ongoing reliability monitoring post-production qualification.
Familiar with process flows specifications and supervising supplier performance (process Cpk yield qualification report etc.)
Possess knowledge on practice of FAI to validate the work suppliers are doing prior to production stage.
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