CPU Design Timing Engineer
CPU Design Timing Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
- Minimum BS and 10 years of relevant experience
- Experience with timing analysis
- Experience with a static timing analysis tool such as PrimeTime or Tempus
- Experience with TCL and either Perl or Python
- Prior experience performing timing analysis in high speed digital designs such as CPUs or other similar designs
- Understanding of physical design tools and methodology including logic synthesis PnR parasitic extraction logic equivalence
- Understanding of deep sub-micron technologies and scaling trends
- Working knowledge of CPU microarchitecture including common fundamental timing paths
- Working knowledge of clock-domain crossing and reset-domain crossing
- Experience with with multiple clock and power domains
- Experience with SDC command usage including clock definitions timing exceptions and IO constraints
- Experience with noise analysis and fixing noise in designs
- Experience with variation modeling in static timing analysis tools
- Experience with RTL modeling and assertion based verification
- Experience with data parsing analysis and representation/plotting
Employment Type
Full Time
