- As a senior member of our SoC physical design team you will be performing various electrical analyses at the block or chip level including but not limited to: Gridcheck ESD Static/Dynamic IR EM Noise and Signal EM.- You will collaborate with the CAD/library/circuit technology/system teams for tech/flow evaluation bring-up validation and qualification for SoC chip development.- You will also work with the implementation team during the entire chip design cycle to drive EMIR test planning analysis support and sign-off closure for tape-out.- You will manage schedules and support cross-functional engineering efforts for the success of Apples SoC product development.
Minimum BS and 10 years of relevant industry experience.
Knowledge of low-power circuit design computer architecture and/or digital systems.
Experience with industrial EDA backend tools including Redhawk PrimeRail Voltus.
Experience with ASIC or AMS physical implementation and analysis flow for IP blocks as well as SoC fullchip.
Proficient in automating and debugging verification flows for digital VLSI design.
Experience with Innovus Design Compiler PrimeTime and Tempus.
Familiar with voltage drop budgeting low-power design techniques and sign-off criteria for solid-state digital circuit systems.
Experience in multiple design tape-outs regarding power integrity signoff.
Disclaimer: Drjobpro.com is only a platform that connects job seekers and employers. Applicants are advised to conduct their own independent research into the credentials of the prospective employer.We always make certain that our clients do not endorse any request for money payments, thus we advise against sharing any personal or bank-related information with any third party. If you suspect fraud or malpractice, please contact us via contact us page.