DDR Design Engineer
DDR Design Engineer
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Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
- BS degree in technical discipline with minimum 10 years of relevant experience.
- RTL design using Verilog or SystemVerilog assertion writing
- Design of state machines data paths arbitration and clock domain crossing logic
- Logic synthesis timing constraints
- Exposure to Design For Test understanding of scan concept and writing DFT friendly RTL
- Unified Power Format for simulation synthesis and electrical rule checking Equivalence checking
- Prior experience in DDR PHY design and mixed-signal environment is a plus
Employment Type
Full Time
