Lead Verification Engineer
Lead Verification Engineer
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Job Description
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Title: Lead Verification Engineer
Location: Montreal Ottawa Toronto
Overview
This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols.
The successful candidate will be a highly motivated self-starter who is able to work independently to complete assigned tasks within required project timelines with high quality.
The candidate will primarily be responsible for the verification of digital RTL and development of re-usable verification components and environments.
It is also expected that the candidate will contribute to all aspects of digital verification including flow development test plan development and execution functional coverage closure and code coverage closure.
The ideal candidate will have a fundamental understanding of the end-to-end verification flow in order to accurately and efficiently communicate with all members of the technical staff regarding overall project development progress and status.
The most successful candidates will be able to demonstrate excellent command of fundamental logic principles as well as excellent problem solving and communication skills.
The candidate should be able to work as part of a small and focused team of engineers and be able to collaborate successfully as needed with design teams verification teams project management and digital and analog design teams in multiple worldwide geographies.
The Candidate should be willing to work full time in the Montreal Quebec Canada office and be willing to travel as required by job function (expectation is 5% travel or less).
Design IP is growing organization within Cadence and our completeIP portfolio can be found here Experience:
- Bachelor of Science in Electrical(EE)/Computer Engineering (CPE) or Computer Science (CSC)
- Understanding of verification architecture and methodologies
- Understanding of Metric Driven Verification
- Understanding of Universal Verification Methodologies
- Understanding of the identification planning and creation of functional coverage and checks
- Understanding of System Verilog Assertions (SVAs)
- Understanding of digital design flow
Preferred Experience:
- Master of Science in EE/CPE/CSC
- Experience with SystemVerilog UVM coding language is desired
- Experience with scripting languages such as Python Perl Ruby Sed or Awk is also strongly preferred
- Exposure to Standard Protocol knowledge for any of the following areas: PCIe USB SATA Ethernet Display Port HDMI
- Exposure to Formal Verification Technologies
- Exposure to Mixed Signal Design experience
- Experience with Cadence tools experience
- Exposure to Low Power verification experience using CPF or UPF
Cadence is an equal-opportunity employer committed to hiring a diverse workforce.
Due to the nature of the role that requires interaction with other entities globally and with employees and stakeholders in other provinces in Canada knowledge of the English language is required for this position.
Titre: Concepteur en Vrification Numrique
Localisation: Montreal Ottawa Toronto
Description:
Cadence Design Systems est la recherche de candidats dexcellence pour joindre une quipe exprimente et dynamique dingnieurs en charge du dveloppement dIP au service des standards de lindustrie.
Le candidat slectionn aura la charge de la vrification de modules numriques RTL et du dveloppement de modules de vrification rutilisables. Le candidat sera aussi amen contribuer toutes les phases du processus de vrification: laboration du plan de vrification codage des points de couverture gnration de stimuli et analyse de couverture.
Le candidat devra possder des connaissances de base des mthodes de design et de vrification des composantes numriques.
Le candidat devra tre autonome dynamique et dmontrer de trs bonnes qualits de communication.
Le groupe de design IP est une quipe multidisciplinaire compose dingnieurs provenant de divers sites travers le monde.
Faisant parti du groupe de vrification le candidat sera amen collaborer avec diverses disciplines et phases de la ralisation complte dIP matriel: design numrique et analogique design physique production etc.
Le groupe de design IP est une organisation grandissante. Le catalogue complet se trouve au site suivant: minimum:
- Baccalaurat en Ingnierie lectrique sciences appliques ou domaine connexe.
- Comprhension des principes de base de la vrification de composantes numriques.
- Comprhension de base de la vrification bases sur les mtriques (Metric Driven Verification).
- Connaissance des Mthodes de Vrification Universelles (UVM).
- Connaissance du langage dassertions SystemVerilog (SVAs).
- Comprhension de base du flot de design numrique.
- Capable de communiquer en anglais.
Exprience recherche:
- Matrise en gnie lectrique sciences appliques ou domaine connexe.
- Exprience avec le langage de vrification SystemVerilog UVM.
- Exprience avec diffrents langages de script tel que Python Perl Ruby etc.
- Connaissance de base des protocoles de transfert de donnes tel que PCIe USB SATA Ethernet Display Port HDMI.
- Connaissance de base des techniques de vrification formelle.
- Connaissance de base des composantes mixtes (analogiques/numriques).
Cadence est une employeuse qui souscrit lgalit des chances et qui sengage embaucher une main-doeuvre diversifie.
Were doing work that matters. Help us solve what others cant.
We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process we encourage you to make your needs known.
Employment Type
Full-Time
