Analog Layout Design Engineer
Analog Layout Design Engineer
Employer Active
Job Alert
You will be updated with latest job alerts via email
Share
Job Alert
You will be updated with latest job alerts via email
Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
Job location: Santa Clara CA 95054
Job Duration: 3 Months Contract to Hire
Job Description:
- Experience with layout of cutting-edge high-performance high-speed CMOS integrated circuits in older foundry CMOS process nodes in 40nm 55nm 65nm and 130nm following best practices from the industry.
- Reviewing and analyzing floorplans and complex circuits with circuit designers
- Running complete set of design verification tools available on AMS blocks
- Interpreting LVS DRC and ERC reports to find the fastest way to complete layout
- Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance area and power requirements
- Be a great role model by inspiring and motivating team and Establishing Effective Organizational Structure and Communication Protocols. Able to Delegate and Empower team along with Effective Time Management.
- Working with the circuit designer or Layout-Lead to plan/schedule work and negotiate any layout trade-offs as needed
- 10 years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3 years of recent experience on advance nodes including FinFET technologies
- Experience with and knowledge of analog/mixed-signal IP (e.g. SERDES PHY transmitter and receiver PLL DDR PHY ADCs DACs LDOs etc.)
- Experience leading complex layout macros during the full design cycle from floorplan analysis to completion of physical design verification
- Great understanding of CAD flows and tools related to analog/mixed-signal layout design
- Experience crafting well-matched low noise and low power analog blocks consisting of transistors resistors capacitors pad IOs ESD structures etc.
- High level of proficiency in custom as well as standard cell-based floorplanning and hierarchical layout assembly
- Must understand issues of IR drop RC delay electro-migration self-heating and coupling capacitance
- Must recognize failure prone circuit and layout structures have experience with analog and DFM standard methodologies and enthusiastically work with circuit designer or layout lead for the best approach to problems
- High level of proficiency in interpretation of CALIBRE DRC ERC LVS etc. reports
- Knowledge of CADENCE or MENTOR GRAPHICS layout tools.
- Excellent interpersonal skills and able to work with remote teams
- Synopsys/Cadence/Mentor Layout tools (Preference: 5)
- Python (Preference: 3)
- TSMC 7nm or 5nm (Preference: 3)
- TSMC 3nm (Preference: 5)
Employment Type
Full-time
