Design Verification Engineer
Design Verification Engineer
Posted on :
14-07-2025
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1 Vacancy
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Job Description
Hiring for One of Our Client
Job Title: Senior / Lead Design Verification Engineer
Experience: 6 10 years
Location: Siruseri Chennai (Work from Office only)
Industry: Semiconductor / VLSI
Employment Type: Full-time / Permanent
Experience: 6 10 years
Location: Siruseri Chennai (Work from Office only)
Industry: Semiconductor / VLSI
Employment Type: Full-time / Permanent
Key Responsibilities:
- Perform functional verification at block and chip level for complex ASIC/SoC designs.
- Build UVM-based testbenches from scratch for new IPs or subsystems.
- Develop and execute detailed verification test plans based on design specifications.
- Write directed and constrained-random test cases; debug simulation failures.
- Perform coverage analysis (functional and code) and drive closure.
- Work with RAL (Register Abstraction Layer) to verify register-level functionality.
- Develop and validate assertions (SVA) for protocol and functional correctness.
- Collaborate closely with RTL DFT and GLS teams to ensure alignment acrossdesign phases.
- Participate in multiple tapeouts ensuring verification quality and delivery.
Required Skills:
- Strong hands-on experience with SystemVerilog and UVM methodology.
- Solid knowledge of SoC/ASIC architecture and verification lifecycle.
- Hands-on experience in writing testbenches stimulus checkers monitors and scoreboards .
- Strong debugging skills using simulation tools like VCS Questa.
- Experience with functional and code coverage.
- Familiarity with Register Abstraction Layer (RAL) modeling and verification.
- Excellent analytical and problem-solving skills.
- Strong communication and teamwork abilities.
Interested candidates kindly forward your resumr to
Employment Type
Full-time
Key Skills
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