Verification Engineer
Verification Engineer
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Job Description
Responsibilities
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Define and implement IP/SoC verification plans build verification test benches to enable IP/sub-system/SoC level verification
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Develop functional tests based on verification test plan
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Drive Design Verification to closure based on defined verification metrics on test plan functional and code coverage
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Debug root-cause and resolve functional failures in the design partnering with the Design team
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Collaborate with cross-functional teams like Design Model Emulation and Silicon validation teams towards ensuring the highest design quality
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Develop and drive continuous Design Verification improvements using the latest verification methodologies tools and technologies from the industry
Minimum Qualifications
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B.S or M.S degree in Electrical Engineering Computer Engineering or Computer Science
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Hands-on experience in Verilog SystemVerilog C/C based verification and UVM methodology
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Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
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Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Employment Type
Full-time
