Sr. SOC Design - STA, Hardware Compute Group
Sr. SOC Design - STA, Hardware Compute Group
Posted on :
13-07-2025
Employer Active
1 Vacancy
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Yearly Salary
$ 143300 - 247600
Vacancy
1 Vacancy
Posted on :
13-07-2025
Job Description
The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Design-STA Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.
Work hard. Have fun. Make history.
Key job responsibilities
Includes definition and development of signoff methodology and corresponding implementation solution
Flow for STA Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs.
Full chip timing constraints development full chip / Sub-System STA and Signoff for a complex multi-clock multi-voltage SoC.
Streamlining the timing signoff criterions timing analysis methodologies and flows.
Analyze and incorporate advance timing signoff flows (AOCV POCV Based STA IR Drop aware STA) into SoC timing signoff flow.
Work for Systems and Architecture SoC Integration Verification DFT Mixed Signal IP owners Synthesis Place & Route and other local/remote teams to address the design challenges in the context of timing sign-off.
Concepts of CRPR clock paths analysis and tweaks to meet timing.
Multi Corner and Multimode analysis.
Close timing at Signoff corners covering the entire modes delay corners for cells and interconnects.
Bachelors degree or higher in EE CE or CS
10 years or more of practical semiconductor implementation experience
Scripting experience with Perl Python tcl shell and drive to automate flows
Proficiency in chip front-end and back-end implementation tools such as Fusion compiler Design Compiler ICC2 or Innovus and Primetime Tempus
Must have good communication and analytical skills.
Should be able to work closely with IP Design teams and Backend Physical Design teams across multiple sites.
PhD in Computer Science Electrical Engineering or related field
Experience with memory compiler
Experience with formal equivalence Cadence Conformal/Synopsys Formality
Have in depth knowledge of entire design process from Design specification defining architecture micro-architecture RTL design and functional verification
Experience with DFT and DFM flows
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status disability or other legally protected status.
Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees supervisors and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees supervisors and staff to ensure exceptional customer service; and follow all federal state and local laws and Company policies. Criminal history may have a direct adverse and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above as well as the abilities to adhere to company policies exercise sound judgment effectively manage stress and work safely and respectfully with others exhibit trustworthiness and professionalism and safeguard business operations and the Companys reputation. Pursuant to the Los Angeles County Fair Chance Ordinance we will consider for employment qualified applicants with arrest and conviction records.
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process including support for the interview or onboarding process please visit for more information. If the country/region youre applying in isnt listed please contact your Recruiting Partner.
Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $143300/year in our lowest geographic market up to $247600/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge skills and experience. Amazon is a total compensation company. Dependent on the position offered equity sign-on payments and other forms of compensation may be provided as part of a total compensation package in addition to a full range of medical financial and/or other benefits. For more information please visit This position will remain posted until filled. Applicants should apply via our internal or external career site.
Work hard. Have fun. Make history.
Key job responsibilities
Includes definition and development of signoff methodology and corresponding implementation solution
Flow for STA Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs.
Full chip timing constraints development full chip / Sub-System STA and Signoff for a complex multi-clock multi-voltage SoC.
Streamlining the timing signoff criterions timing analysis methodologies and flows.
Analyze and incorporate advance timing signoff flows (AOCV POCV Based STA IR Drop aware STA) into SoC timing signoff flow.
Work for Systems and Architecture SoC Integration Verification DFT Mixed Signal IP owners Synthesis Place & Route and other local/remote teams to address the design challenges in the context of timing sign-off.
Concepts of CRPR clock paths analysis and tweaks to meet timing.
Multi Corner and Multimode analysis.
Close timing at Signoff corners covering the entire modes delay corners for cells and interconnects.
Bachelors degree or higher in EE CE or CS
10 years or more of practical semiconductor implementation experience
Scripting experience with Perl Python tcl shell and drive to automate flows
Proficiency in chip front-end and back-end implementation tools such as Fusion compiler Design Compiler ICC2 or Innovus and Primetime Tempus
Must have good communication and analytical skills.
Should be able to work closely with IP Design teams and Backend Physical Design teams across multiple sites.
PhD in Computer Science Electrical Engineering or related field
Experience with memory compiler
Experience with formal equivalence Cadence Conformal/Synopsys Formality
Have in depth knowledge of entire design process from Design specification defining architecture micro-architecture RTL design and functional verification
Experience with DFT and DFM flows
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status disability or other legally protected status.
Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees supervisors and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees supervisors and staff to ensure exceptional customer service; and follow all federal state and local laws and Company policies. Criminal history may have a direct adverse and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above as well as the abilities to adhere to company policies exercise sound judgment effectively manage stress and work safely and respectfully with others exhibit trustworthiness and professionalism and safeguard business operations and the Companys reputation. Pursuant to the Los Angeles County Fair Chance Ordinance we will consider for employment qualified applicants with arrest and conviction records.
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process including support for the interview or onboarding process please visit for more information. If the country/region youre applying in isnt listed please contact your Recruiting Partner.
Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $143300/year in our lowest geographic market up to $247600/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge skills and experience. Amazon is a total compensation company. Dependent on the position offered equity sign-on payments and other forms of compensation may be provided as part of a total compensation package in addition to a full range of medical financial and/or other benefits. For more information please visit This position will remain posted until filled. Applicants should apply via our internal or external career site.
Required Experience:
Senior IC
Employment Type
Full-Time
Key Skills
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