Design Verification Lead Engineer
Design Verification Lead Engineer
Employer Active
Job Alert
You will be updated with latest job alerts via email
Share
Job Alert
You will be updated with latest job alerts via email
Job Description
Role: Design Verification Lead Engineer
Location: Austin TX (Hybrid negotiable no remote)
Type: Contract
Interview: Phone/Skype
Were looking for a strong Lead DV Engineer with 10 years in SoC verification across ARM ecosystems. Must be hands-on with C/SystemVerilog UVM PCIE/DDR GLS GIT and experienced in debugging team mentorship and verification flows. Required tools: Synopsys/Cadence SpyGlass Simvision.
#DesignVerification #SystemVerilog #UVM #PCIE #DDR #ARMVerification #SpyGlass #Simvision #Python #Cadence #SOCVerification #C2CHiring
Additional Information :
All your information will be kept confidential according to EEO guidelines.
Remote Work :
No
Employment Type :
Contract
Employment Type
Contract
