FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible with the ultimate goal ofenabling human life on Mars.

FPGA/ASIC DESIGN ENGINEER (SILICON ENGINEERING)

At SpaceX were leveraging our experience in building rockets and spacecraft to deploy Starlink the worlds most advanced broadband internet system. Starlink is the worlds largest satellite constellation and is providing fast reliable internet to millions of users worldwide. We design build test and operate all parts of the system thousands of satellites consumer receivers that allow users to connect within minutes of unboxing and the software that brings it all together. Weve only begun to scratch the surface of Starlinks potential global impact and are looking for best-in-class engineers to help maximize Starlinks utility for communities and businesses around the globe.

We are seeking a motivated proactive and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems firmware architecture design validation product engineering ASIC implementation). In this role you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

• Design digital ASICs and/or FPGAs for Starlink projects implementing complex SoC blocks and SoC integration tasks
• Implement or integrate design blocks using Verilog/SystemVerilog
• Optimize designs for power performance and area
• Participate in the design process starting with high-level conceptual and architectural discussions and ending with micro architecture and design partition within the ASIC and/or FPGA
• Participate in all phases of ASIC and/or FPGA design flow (e.g. synthesis timing closure verification)
• Work with ASIC backend/implementation teams as needed
• Bring-up and validate ASICs and FPGAs in the lab
• Collaborate with software engineers in developing production software for your designs

BASIC QUALIFICATIONS:

• Bachelors degree in electrical engineering computer engineering or computer science
• 2 years of experience working with ASICs or FPGAs

PREFERRED SKILLS AND EXPERIENCE:

• Experience designing digital ASICs and/or FPGAs
• Experience writing RTL in Verilog or SystemVerilog
• Experience in designing SoC DSP digital communication system datapath blocks and/or modems
• Experience and understanding of AXI/AHB/APB protocols
• Experience with EDA tools such as HDL simulators (e.g. VCS Questa IES) HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado Altera Quartus II)
• Experience with scripting (csh/bash Perl Python etc.)
• Software design and development skills
• Ability to work in a dynamic environment with changing needs and requirements
• Team-player can-do attitude and ability to work well in a group environment while still contributing on an individual basis
• Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION & BENEFITS:

Pay range:

ASIC/FPGA Design Engineer/Level I: $120000.00 - $145000.00/per year
ASIC/FPGA Design Engineer/Level II: $140000.00 - $170000.00/per year

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills education and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives in the form of company stock stock options or long-term cash awards as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical vision and dental coverage access to a 401(k) retirement plan short & long-term disability insurance life insurance paid parental leave and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

ITAR REQUIREMENTS:

• To conform to U.S. Government export regulations applicant must be a (i) U.S. citizen or national (ii) U.S. lawful permanent resident (aka green card holder) (iii) Refugee under 8 U.S.C. 1157 or (iv) Asylee under 8 U.S.C. 1158 or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit competence and qualifications and will not be influenced in any manner by race color religion gender national origin/ethnicity veteran status disability status age sexual orientation gender identity marital status mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceXs Affirmative Action Plan for veterans and individuals with disabilities or applicants requiring reasonable accommodation to the application/interview process should reach out to.