Position: STA Engineer-
Location: San Jose CA (Day-1 Onsite)
Interview: video
Duration: 12 months
- Must have/Primary skills: Fullchip timing SDC changes back to block level Block/Full chip SDC development Static Timing Analysis Primetime/Tempus
What Youll Be Doing:
- Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
- Option to also do block level RTL design or block or top-level IP integration.
- Helping develop efficient methodology to promote block level SDCs to fullchip and to bring fullchip SDC changes back to block level.
- Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
- Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
- Creating fullchip clocking diagrams and related documentation.
What We Are Looking For:
- Bachelors Degree in Electrical or Computer Engineering with 7 years of ASIC or related experience or Masters Degree in Electrical or Computer Engineering with 5 years of ASIC or related experience.
- Experience with block/full chip SDC development in functional and test modes.
- Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
- Understanding of related digital design concepts (eg. clocking and async boundaries)
- Experience with synthesis tools (eg. Synopsys DC/DCG/FC) Verilog/System Verilog programming
- Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence)
- Experience with Spyglass CDC and glitch analysis
- Experience using Formal Verification: Synopsys Formality and Cadence LEC.
- Experience with scripting languages such as Python Perl or TCL
Thank You
Mridula Sahni
Sr. Delivery Manager
Pro Integrate LLC ISO 9001 and ISO 27001 Certified Company
Phone: 1 Email:
HQ: 347 5th Ave Suite 1402-344 New York NY USA 10016