Staff ASIC Design Engineer â AI/ML Hardware IP
Staff ASIC Design Engineer â AI/ML Hardware IP
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Job Description
Position: Staff ASIC Design Engineer AI/ML Hardware IP
Location: On-site in Canada
Were partnering with a leading global semiconductor company to find a Staff ASIC Design Engineer to help architect and develop next-gen AI/ML hardware IP. This role is ideal for someone who thrives in RTL design micro-architecture development and hardware integration particularly in areas like clock domain crossing power optimization and formal verification.
Key Responsibilities:
Define micro-architecture and detailed specifications from high-level design requirements.
Develop performance-optimized RTL design (Verilog/SystemVerilog) with strong area and power efficiency.
Integrate sub-IP blocks into larger SoC components and subsystems.
Conduct Lint CDC and synthesis flow analysis.
Collaborate with verification teams to define test plans debug regressions and analyze coverage reports.
Create SVA assertions for white-box and formal verification.
Communicate effectively across cross-functional teams to ensure timely execution of deliverables.
What Theyre Looking For:
5 years of hands-on ASIC design experience (verification RTL integration etc.).
Proficiency in Verilog/SystemVerilog RTL design and logic synthesis.
Experience with one or more of the following:
Clock/reset architecture FIFOs bus protocols (AHB/AXI) memory control
AI/ML hardware blocks
Power-aware design using UPF CLP PowerPro etc.
CDC and lint tools (Spyglass 0-in SVA)
Synthesis and timing tools (Design Compiler PrimeTime Formality)
Simulation tools (VCS Verdi Questa Xcelium)
Scripting in Python Perl TCL or C
Required Education/Experience:
Bachelors (with 5 years) Masters (3 years) or PhD (2 years) in Electrical Engineering Computer Engineering or related field.
Legally authorized to work on-site in Canada.
Required Experience:
Staff IC
Employment Type
Full-Time
