Senior IC Design Engineer (PLL and Clock Distribution expertise)
Senior IC Design Engineer (PLL and Clock Distribution expertise)
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Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
San Diego CA (onsite/hybrid)
US Citizen or US Permanent Resident (preferred)
Full-Time Health Benefits 401K Plan PTO Founder Shares
Requirements:
High-speed time-interleaved ADCs (SAR pipeline TDC etc.) RF front-end design SerDes miscellaneous functions (other data converters filters amplifiers PLLs power management oscillators etc.) in FinFET technologies.
MS with 5 years or PhD with 3 years of experience preferred.
Strong PLL and clock distribution experience is preferred
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Javier Leon
cell
(are we connected)
Required Experience:
Senior IC
Employment Type
Full Time
