Design Verification Engineer, Senior Staff
Design Verification Engineer, Senior Staff
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Salary Not Disclosed
1 Vacancy
Job Description
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
Marvell switching solutions have been driving a change in networks by delivering a stream of technical innovations through a broad portfolio of segment-focused Ethernet switch product families. Marvell switching technology is powering the next generation of borderless and secure networks. Marvell is addressing the surge of the data economy data centers provide critical infrastructure from the cloud to the edge. Marvell Prestera and Teralynx switches provide the bandwidth scale for every application with advanced packet processing and analytics to address the most demanding needs.What You Can Expect
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- Develop the architecture for a functionalverificationenvironment including reference models and bus-functional monitors and drivers.
- Work closely with architects/RTL engineers to bring-up a newarchitecture/micro-architectureon theverificationenvironment.
- Develop testbench components in Systemverilog UVM C and C. Write tests in Systemverilog UVM C C python to test various logical features in ASIC and SOC design blocks.
- Debug failures in tests and root cause issues with test environment and design.
- Write averificationtest plan using random techniques and coverage analysis and work with designers to ensure it is complete.
- Develop tests and tune the environment to achieve coverage goals.
- Own and debug failures in simulation to root cause problems
- Architecting developing and maintaining tools to streamline the design of state-of-the-art multicore SoCs.
- Analysis/closure of code and functional coverage.
What Were Looking For
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- Bachelors degree in Computer Science Electrical Engineering or related fields and 5 years of related professional experience.
- Masters degree and/or PhD in Computer Science Electrical Engineering or related fields with 3 years of experience.
- Experience with functional verification techniques.
- Strong understanding of digital design principles and methodologies.
- Hands-on experience on using Verilog System Verilog and C
- Understanding of Ethernet networking.
- Excellent problem-solving and debugging skills.
- Effective communication and collaboration skills.
- Ability to work in a fast-paced dynamic environment.
Expected Base Pay Range (USD)
124420 - 186400 $ per annumThe successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell we offer a total compensation package with a base bonus and and financial wellbeing are part of the package. That means flexible time off 401k plus a year-end shutdown floating holidays paid time off to volunteer. Have a question about our benefits packages - health or financial Ask your recruiter during the interview process.All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .
#LI-TM1Required Experience:
Senior IC
Employment Type
Full-Time
