Senior Manager Verification Engineer
Senior Manager Verification Engineer
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Job Description
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
Marvell is empowering the global data economy. Whether at the network core or edge our leadership technologies make it possible for the worlds data to be processed moved stored and secured faster and more reliably. With leading intellectual property and deep systemlevel knowledge Marvells infrastructure semiconductor solutions are transforming the 5G cloud computing enterprise and automotive markets of tomorrow. Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading edge high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast-growing product lines Marvell technology is powering the next-generation data processing and workload acceleration platforms for multiple market segments.What You Can Expect
- Lead DV efforts for blocks subsystems and top-level verification.
- Develop and maintain UVM-based verification environments.
- Define and review test plans with architecture and design teams.
- Verify designs using directed and constrained random techniques.
- Maintain regression debug failures and analyze coverage.
- Drive verification to meet coverage targets.
- Contribute to next-gen data processing and hardware accelerator verification.
- Focus on networking domain verification for future solutions.
- Ensure design closure using innovative and automated techniques.
What Were Looking For
- Bachelors or Masters degree in Computer Science Electrical Engineering or a related field with 8 years of professional experience.
- Strong experience with Verilog SystemVerilog and UVM.
- Expertise in unit and subsystem verification modern verification concepts.
- Proficiency in SystemVerilog C C and scripting (Perl Tcl Python preferred).
- Strong debugging skills and verification flow optimization.
- Collaborate with design teams on specs test plans and verification strategies.
- Develop and maintain UVM-based testbenches for ASIC SoCs.
- Execute verification maintain regressions and debug failures.
- Excellent verbal and written communication skills.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
#LI-KP1Required Experience:
Senior Manager
Employment Type
Full Time
