Analog Layout Design Engineer
Analog Layout Design Engineer
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1 Vacancy
Job Description
Role: Analog Layout Design Engineer
Location: Santa Clara CA (Onsite)
Employment Type: Contract
Interview: Phone/Skype
Job Description:
Looking for an experienced Analog Layout Design Engineer with expertise in CMOS FinFET technologies (7nm 3nm) highspeed IC layout and EDA tools.
Analog & RF Layout for HighSpeed Applications
UltraLow Power ASIC/SOC Design
EDA Tools: Cadence Mentor Synopsys
MixedSignal Layout (TIAs CMOS Drivers Data Converters PLLs)
Python Scripting & Floor Planning
#AnalogDesign #RFLayout #CMOSFinFET #EDA #Python #Cadence #MentorGraphics #Synopsys
Additional Information :
All your information will be kept confidential according to EEO guidelines.
Remote Work :
No
Employment Type :
Contract
Employment Type
Contract
