Microelectronics Packaging Engineer (Associate, Mid-Level or Lead)

Microelectronics Packaging Engineer (Associate MidLevel or Lead)

Company:

The Boeing Company

Boeing Research & Technology (BR&T) is current looking for a Microelectronics Packaging Engineer (Associate MidLevel or Lead) to join the team based in Huntington Beach CA.

We are Boeing Research & Technology (BR&T): Boeings global research and development team creating and implementing innovative technologies that make the impossible possible and enable the future of aerospace. We are engineers and technicians skilled scientists and bold innovators; Join us and put your passion determination and skill to work building the future!

#TheFutureIsBuiltHere #ChangeTheWorld

BR&T Microelectronics Technology (MET) team performs microelectronics technology development and design for aerospace systems. We develop digital analog and RF Systems on Chip (SoCs) for radar navigation electronic warfare communications processing and other electronic systems. These systems are used on Boeing airborne terrestrial and satellite platforms.

The Boeing Research and Technology team is seeking an innovative Microelectronics Packaging Engineer (Associate MidLevel Senior) to join our Microelectronics Technology team in Huntington Beach CA.

This packaging engineer will have a strong background in the current stateoftheart for advanced microelectronics and semiconductor packaging. The successful candidate will participate in and lead the innovation and development of novel 2.5D / 3DHI advanced packaging for highspeed/mixed signal/RF microelectronics applications inclusive of electrical performance of both active and passive elements thermalmechanical performance and design for manufacturability and reliability. Designs are implemented with stateoftheart semiconductor process technologies including CMOS GaAs GaN and SiGe. SSED using external wafer fabrication teams. Our team has numerous microelectronics projects funded both by internal Boeing customers and external Government Science and Technology (S&T) customers. Join us and put your passion determination and skill into working and building the future!

Position Responsibilities:

• Conducts advanced packaging analysis based on system requirements development of architectural approaches and detailed specifications
• Resolves complex issues on critical programs related to advanced packaging approaches requirements specifications and design
• Designing and optimizing layout for advanced substrates of HDI IC substrate Silicon or LTCC substrates considering electrical thermal and mechanical requirements.
• Collaborate in multifunctional discussions for package architecture and technology roadmap (partner with Silicon IC team)
• Crossfunctional interface with IC design materials SI/PI thermal systems and production teams to optimize package solutions on cost performance manufacturability and reliability
• Interface with packaging assembly and substrate suppliers for new product bringup qualification and production ramp
• Optimize package pinouts by evaluating systemlevel tradeoffs Conduct package routing placement stackup reference plane and power distribution activities
• Conduct design feasibility studies to assess package design goals encompassing size cost and performance
• Develop symbols and CAD library databases using Cadence APD or Mentor Xpedition tools
• Works under minimal direction

Basic Qualifications (Required Skills/Experience):

• Ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret clearance PostStart is required
• Bachelor of Science degree from an accredited course of study in engineering engineering technology (includes manufacturing engineering technology) chemistry physics mathematics data science or computer science
• Experience with EDA tool flow and vendor supports including but are not limited to chiplets floorplanning interposer design SiP optimization physical simulation and chiplets assembly
• Handson experience with package design and proficient in Cadence Allegro platform tools (PCB Editor Advanced Package Designer APD/SiP) or Mentor Xpedition platform tools

Preferred Qualifications (Desired Skills/Experience):

• Active security clearance
• 5 years of related work experience or an equivalent combination of education and internship experience
• Experience with 3DIC development flow and tools; chiplevel and substrate requirements architecture design and verification; foundry interface and fabrication; and final characterization and test including electrical mechanical and thermal considerations
• Experience with TSV 2D/2.5D and 3D package connection
• Handson expertise of advanced and new assembly processes for flipchip wirebond and MCM packages
• SI/PI tools (XtractIM PowerSI HFSS Q3D etc.) package model extraction Sparameters and RLGC model
• Substrate manufacturing process structure design rules and material property
• Solid understanding of highspeed interfaces including DDR PCIe NAND etc
• Consistent track record to drive package selection through feasibility studies and drive chip Floor planning and bump assignment
• Familiar with package design reviews and familiarity with CAM350/Valor or Calibre and CAD
• Knowledge of highspeed layout constraints (crosstalk mitigation differential pairs EMI/RFI PCB/package resonance)
• Familiar with Cadence Concept HDL for schematic review experience in schematic capture and system integration
• Experience in advanced node IC layouts such as 22nm 16nm 7nm 5nm or below
• Experience in layout of sensitive RF blocks such as low noise amplifiers voltage controlled oscillators and mixers
• Understanding of layout considerations for device matching coupling and noise isolation
• Knowledge of advanced substrate manufacturing/process
• Knowledge of failure analysis techniques on advanced node silicon products
• Conceptual knowledge of package cost structure
• Knowledge of GD&T and be able to read/comprehend mechanical drawings
• Excellent oral and written communication skills and ability to communicate across multiple disciplines with internal and external customers
• Computer proficiency and ability to use and navigate the internet and various computer software programs (e.g. Microsoft Office Suite)
• Skill and ability to collect organize synthesize and analyze data; summarize findings; develop conclusions and recommendations from appropriate data sources

Pay & Benefits:

At Boeing we strive to deliver a Total Rewards package that will attract engage and retain the top talent. Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.

The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs generally including health insurance flexible spending accounts health savings accounts retirement savings plans life and disability insurance programs and a number of programs that provide for both paid and unpaid time away from work.

The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location date of hire and the applicability of collective bargaining agreements.

Pay is based upon candidate experience and qualifications as well as market and business considerations.

Summary pay range for Associate: $85850.00 $116150.00

Summary pay range for MidLevel: $104550.00 $141450.00

Summary pay range for Lead: $126650.00 $171350.00

Language Requirements:

Not Applicable

Education:

Bachelors Degree or Equivalent

Relocation:

This position offers relocation based on candidate eligibility.

Export Control Requirement:

This position must meet export control compliance requirements. To meet export control compliance requirements a U.S. Person as defined by 22 C.F.R. 120.15 is required. U.S. Person includes U.S. Citizen lawful permanent resident refugee or asylee.

Safety Sensitive:

This is not a Safety Sensitive Position.

Security Clearance:

This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Top Secret/SCI Clearance PostStart is required.

Visa Sponsorship:

Employer will not sponsor applicants for employment visa status.

Contingent Upon Award Program

This position is not contingent upon program award

Shift:

Shift 1 (United States of America)

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