STA
Posted on :
16-05-2025
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1 Vacancy
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Job Description
Responsibilities:
* Responsible for leading a team of STA engineers and closing highfrequency lowertech node complex designs.
* Conduct fullchip timing analysis from early investigation to final implementation and tapeout.
* Propose or develop timing methodologies to support the timing flow from RTL synthesis to implementation and timing closure.
* Work with architects and logic designers to generate block and fullchip timing constraints.
* Analyze scenarios and margin strategies with the Synthesis & Design team.
* Partner with physical design teams to close and sign off the designs through PnR (Place and Route) and ECO (Engineering Change Order) cycles.
* Work with the physical design team to improve interface and clock latency.
* Develop SDC constraints for blocks partitions and fullchip including define constraints IO budgeting and merging constraints.
* Collaborate with thirdparty IP providers to derive timing signoff requirements.
Requirements:
* Bachelors or Masters degree in Electrical Engineering or Electronics & Communications.
* 3 years of experience in STA (Static Timing Analysis).
* Handson experience in ASIC timing constraints generation and timing closure.
* Expertise and advanced knowledge of industrystandard timing EDA tools (Prime Time StarRC Tempus Tweaker etc..
* Deep understanding and experience in timing closure of various functional and test modes.
* Expertise in deepsubmicron processes including Crosstalk delay noise glitch AOCV/SOCV/POCV and STA.
* Proficiency in industrystandard EDA tools from Cadence Synopsys and Mentor Graphics for Synthesis PnR and Signoff Closure.
* Strong scripting skills using TCL Python or Perl for design automation and tool customization.
* Excellent problemsolving and analytical skills with a track record of delivering highquality designs on schedule.
* Outstanding communication and interpersonal skills with the ability to collaborate effectively in a team environment.
* Efficient written and verbal communication excellent organization skills and mentorship qualities.
* Ability to work crossfunctionally with various teams and be productive under aggressive schedules.
* Proven ability to lead and mentor junior engineers fostering their professional growth and development.
static timing analysis,prime time,eda tools,tweaker,sta,socv,tcl,eda,tempus,noise glitch,scripting,cadence,starrc,pocv,crosstalk delay,python,asic timing constraints generation,perl,deep-submicron processes,asic,aocv,timing closure
Employment Type
Full Time
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