Design Verification Intern
Design Verification Intern
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Job Description
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
Seeking Design Verification engineer who canunderstand Design specification and develop test/coverage plan. Development ofconstrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals.
Job Description
Understand Design specification and develop test/coverage plan. Development ofconstrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals.
Required experience.
- Understanding of SV/UVM.
- Good knowledge of Verilog/Vhdl/C/C
- Experience in any scripting language Perl/Python/Shell.
- Good debugging skills.
Desirable skills and experience
- Familiarity with ARM/CPU architectures.
- Good knowledge of some of the protocols like UART I2C SPI JTAG
- Knowledge of AMBA protocols. (AXI/AHB/APB).
- Hands on experience in writing tests/sequences/functional coverage.
- Prior experience with Cadence verification tools and flows is highly desirable.
Strong vocabulary communication planning and presentation skills are essential. Ability to work with high quality output and results in a fast paced and dynamic environment. Ability and desire to learn newmethodologies languages protocols etc. Must be open to constant personal development and growth to meet the evolving demands of the semiconductor industry. Selfmotivated and willing to take up additional responsibilities to contribute to teams success.
Were doing work that matters. Help us solve what others cant.
Required Experience:
Intern
Employment Type
Full-Time
