ASIC Formal Verification Engineer - Annapurna, Annapurna Labs

In Annapurna Labs we are at the forefront of hardware codesign not just in Amazon Web Services (AWS) but across the industry. The work we do is cuttingedge and internetscale while also being deeply important to our customers. We design and build every component of our hardware and software to come together into products that our customers use for accelerated computing: either Machine Learning acceleration or FPGA acceleration. We get our hands dirty from creating our own silicon pushing the electrons in the right direction ensuring our hardware is functional and healthy and managing the full lifecycle of our systems at the huge scale and complexity of AWS. If youre interested in building a complete product from inception to delighted customers Annapurna is a fantastic choice.
As a member of the Machine Learning Acceleration team you will be responsible for defining and checking the specification of critical hardware modules using formal methods and industrial model checkers.
You will be a part of a world class presilicon hardware design team. The job entails understanding requirements of specific hardware blocks and writing functional descriptions of correct behavior. Specifications are written in hardware description languages like Verilog and System Verilog Assertions (SVA). Using industrial model checkers you will then learn techniques for proving the hardware being designed matches the modeled specification. Advances proof techniques such as modeling abstractions and inductive reasoning will be utilized. Automation techniques and scripting flows are also leveraged to accelerate proof techniques.
About the team
Mentorship & Career Growth
Our team is dedicated to supporting new team members in an environment that celebrates knowledge sharing and mentorship. Projects and tasks are assigned in a way that leverages your strengths and helps you further develop your skillset.
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Work/Life Harmony
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To qualify applicants should have earned (or will earn) a Bachelors or Masters degree between December 2022 and September 2025.
Completed coursework or prior internship experience with formal methods (SW/HW)
Coursework or prior internship experience in the basics of computer architecture.

Experience or previous technical internship(s) with hardware model checkers: JasperGold or VC Formal.
Experience or previous technical internship(s) with RTL: Verilog or VHDL.
Knowledge of declarative programming languages: Ocaml Haskell.
Experience with scripting languages such as Python or TCL.
Ability to effectively articulate technical challenges and solutions
Adept at handling ambiguous or undefined problems as well as ability to think abstractly

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